A conventional multi-core processor system includes a symmetric multiple processor (SMP) that has plural cores of the same type and an asymmetric multiple processor (AMP) that has plural cores of different types. Thereby, the development cost may increase and the reliability may be degraded associated with the change of the program code.
In contrast, when a software asset is handed down to the AMP, high-load software are distributed to and executed by cores and consequently, no change occurs to the program code and the performance is improved. The AMP to which the high-load software is distributed includes a low-clock frequency processor core that controls the entire AMP and a high-clock frequency processor core that executes high-load processing within short period. A multi-core processor system having plural processor cores of differing performance is referred to as “heterogeneous multi-core processor system”.
Various power saving techniques are applied to an embedded apparatus such as a mobile telephone to increase the battery life time by reducing the power consumption. Even for the same battery life time, by reducing the power consumption, the battery can be downsized, and the weight and the volume of the entire embedded apparatus can be reduced.
A power saving technique of a heterogeneous multi-core processor system has been disclosed where power saving is facilitated by switching a central processing unit (CPU) to cause a program to operate, corresponding to the load of the CPU (see, e.g., Japanese Laid-Open Patent Publication No. H04-215168).
Another power saving technique of a heterogeneous multi-core processor system has been disclosed where power saving is facilitated by selecting a CPU to which a program is to be assigned, from among a dedicated CPU and a general-purpose CPU according to whether the system is driven by an external power source or a battery (see, e.g., Japanese Laid-Open Patent Publication No. 2008-276395).
A technique is disclosed of facilitating power saving by executing dynamic voltage and frequency scaling (DVFS) control (see, e.g., Kimura, Keiji, et al, “OSCAR API for Real-time Low-Power Multicores and Its Performance on Multicores and SMP Servers”, Department of Computer Science and Engineering, Vol. 2, No. 3, September 2009, pp. 96-106). The “DVFS control” is a technique of reducing the power consumption by reducing as much as possible the voltage and the frequency within the range of the longest allowed program execution restriction time period because the power consumption is proportional to the voltage or the frequency.
However, with the technique according to Japanese Laid-Open Patent Publication No. H04-215168, a leak current is generated from a CPU to which no process is assigned and particularly, when the frequency of the processor is high, the power consumption is increased by the leak current.
With the technique according to Japanese Laid-Open Patent Publication No. 2008-276395, the CPU to which a program is to be assigned is selected according to whether the power source used is an external power source or a battery. When the system is driven by a battery, a CPU is selected whose performance is low and establishes a power saving state. Therefore, a problem arises in that the execution time of the program is always long even when the battery has sufficient power.
With the technique according to Kimura, Keiji, et al, multiple power source voltages are required and dedicated circuits have to be implemented for the voltages. Therefore, a problem arises in that the production cost and the area for implementing the system increase. The technique according to Kimura, Keiji, et al is directed to the state of multiple cores and a single thread. Therefore, when a multi-thread operation is executed, the threads mutually affect one other. Therefore, another problem arises in that estimation of the thread execution ending time is difficult.